Founder

Ciprian Seiculescu

Owner & CEO

About

The research and educational experience of Ciprian Seiculescu is geared towards the fields of embedded software, integrated hardware design and high-level synthesis. During the graduate studies at the Swiss Federal Institute of Technology in Lausanne (EPFL), he studied aspects from the fields of artificial intelligence, advanced computer architecture and hardware synthesis. Later on, during the PhD program at the Swiss Federal Institute of Technology in Lausanne (EPFL) he was involved in researching and developing algorithms for algorithms and tools for High-Level Synthesis (HLS) of on chip interconnect networks. The goal of the algorithms was to generate the optimal Network-on-Chip (NoC) topology for a heterogenous System-on-Chip that met the communication requirements while respecting the constraints of the underlining integration technology.

Education

  • PhD: in Computer Science, July 2012, from Ecole Polytechnique Federale de Lausanne. PhD thesis: “Design Methods and Tools for Application-Specific Predictable Networks-on-Chip”
  • MSc: in Computer Science, January 2008, from Ecole Polytechnique Federale de Lausanne. Graduation project: “Design Framework and Methodology for Synthesis of Networks-On-Chip on FPGA Platforms and 3D Chips”. Grade 5.78 (out of 6).
  • BSc: in Automation and Computer Science, September 2006, from ‘Politehnica’ University of Timisoara, Romania. Graduation project: “3D Multi-Material Printing: Control of the Printing Heads“. Grade 9.81 (out of 10).
  • B737-NG Type rating (Ryanair program) with CAE Oxford Aviation Academy, Amsterdam, Holland, October 2016.
  • Frozen ATPL(A) integrated course with Pilot Training Network/Intrcockpit, Frankfurt, Germany, April 2014. ATPL theory credit average sore 95%.

Engineering and Teaching Experience

  • Owner and CEO at Droid Intelligence SRL, Timisoara, Romania. Feb 2021 – present.
  • Lecturer at University Politehnica of Timisoara, Romania. Feb 2021 – July 2022.
  • External collaborator at Continental Automotive SRL, Timisoara, Romania. May 2021 – present.
  • System architect at Continental Automotive SRL, Timisoara Romania. Sept 2014 – July 2016. ADAS department.
  • Internship with iNoCs Sarl, Lausanne 2008-2012. Collaboration for the PhD research.
  • Teaching and research assistant at  Ecole Polytechnique Federale de Lausanne, Switzerland. Feb 2008 – July 2021.
  • Internship with Fraunhofer IPA in Stuttgart, Germany 2006 (6 months). Development of my BSc graduation project.

Aviation Experience

Work Experience

  • First Officer at Wizz Air, Iasi, June 2022 – present.
  • First officer at Emirates Airlines, Dubai Feb 2020 – June 2020. Made redundant due to Coronavirus downsizing.
  • First officer at Ryanair DAC, London Stansted, Timisoara, Bucharest 2016-2020.

License & Time

  • License: ATPL (A)
  • Total Time: 4172:22
  • B737 Time: 2556:40
  • A320: 1126:00
  • A321: 340:30
Details & Photos

Skills and Knowledge

  • Programming languages: C, C++, C#, Java, Python, Makefile, Assembly
  • Microcontroller families: ARM Cortex-M, RISC-V, MSP, AVR, PIC
  • Programming development tools: Visual Studio .Net, Eclipse, NetBeans, QT, Matlab & Simulink, Android Development Studio, MPLab, STM32Cube, Anaconda, Git, Doxygen.
  • Hardware description languages: VHDL, Verilog, System Verilog.
  • Hardware development tools: Xilinx Vivado, Xilinx Embedded Development Kit (EDK), Xilinx Integrated Software Environment (ISE), Altera Quartus II, ModelSim, Synopsys Design Compiler.
  • System architecture: UML/SysML, Rational Rhapsody, Doors.

General Knowledge

  • Operating systems: Microsoft Windows / Linux (Ubuntu, RHEL, Raspberry PI OS)
  • Office tools: Microsoft Office (Word, Excel, Power point, Outlook), Latex
  • Photo editing: Nikon Capture, Adobe Photoshop Express, GIMP
  • Website design: WordPress

Main publications

  • C. Seiculescu, S. Murali, L. Benini and G. De Micheli. SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, num. 12, p. 1987-2000, 2010.
  • C. Seiculescu, S. Murali, L. Benini and G. De Micheli. Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, num. 5, p. 364 – 368, 2010.
  • C. Seiculescu, S. Murali, L. Benini and G. De Micheli. A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control. Design, Automation and Test in Europe Conference (DATE 2010), Dresden, Germany, 2010.
  • C. Seiculescu, S. Murali, L. Benini and G. De Micheli. NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs. DAC 2009, San Francisco, USA, 2009.
  • C. Seiculescu, L. Benini, and G. De Micheli. A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory, CODES+ISSS’12, October 7-12, 2012, Tampere, Finland.
  • Ciprian Seiculescu, Dara Rahmati, Srinivasan Murali, Hamid Sarbazi-Azad, Luca Benini, and Giovanni De Micheli: Designing best effort networks-on-chip to meet hard latency constraints. ACM Trans. Embedded Comput. Syst. 12(4): 108 (2013)
Full publication list

Languages

  • Romanian: native speaker.
  • English: fluent.
  • German, French: basic.

Interests & Hobbies

  • Photography
  • Astronomy
  • Hiking
Selected photos

Scroll to Top